Circuits for converting the effective value of input electric signals into dc voltages

ABSTRACT

A circuit for converting the effective value of an input electric signal into a DC voltage comprises an integrator for producing a DC output voltage, a first means for adding the input signal to a signal fed back from the output side of the integrator, a second means for subtracting the signal fed back from the output of the integrator from the input signal, and means for multiplying the output from the first means with the output from the second means for applying the product to the input of the integrator.

United States Patent Nakane et alt [54] CIRCUITS FOR CONVERTING THE EFFECTIVE VALUE OF INPUT ELECTRIC SIGNALS INTO DC MULTIPLIER ADDER SiGN [ 51 Mar.28,1972

,[56] References Cited UNITED STATES PATENTS 2,822,474 2/1958 Boecker ..328/26 I Primary Examiner-John Zazworsky Attorney-Chittick, Pfund, Birch, Samuels & Gauthier [5 7] ABSTRACT A circuit for converting the effective value of an input electric signal into a DC voltage comprises an integrator for producing a DC output voltage, a first means for adding the input signal to a signal fed back from the output side of the integrator, a second means for subtracting the signal fed back from the output of the integrator from the input signal, and means for multiplying the output from the first means with the output from the second means for applying the product to the input of the integrator.

8 Claims, 3 Drawing Figures INTEGRMUH E u o PATENTEDMARZB 1972 3, 652.945

sum 1 OF 2- 'FIGJ HUHIPLIER INTEGMIUR IUUIPUER INTEGRHBR SIGN INVERTUB INVENTOR 8 HI SAO NAKANE AKIHISA HASHIMO'I'O ATTORNEY S PATENTEDMAR28 m2 3.652.945

SHEET 2 0r 2 SIGN INVERTUR mvzzwrok HI SAO NAKANE AKIHISA HASHIMOTO ATTORNEY CIRCUITS FOR CONVERTING THE EFFECTIVE VALUE OF INPUT ELECTRIC SIGNALS INTO DC VOLTAGES BACKGROUND OF THE INVENTION This invention relates to a circuit for converting the effective value of an input electric quantity into a DC voltage.

In one example of the prior circuits for converting the efi'ective value of an input electric quantity into a DC voltage, the input electric quantity is first squared and then the square root of the mean value is extracted, whereas in another example, the input electric quantity is passed through a heating wire and the quantity of the heat generated is measured by a thermocouple. However, it is troublesome to square the input signal and then to extract the square root of the mean value. Further, since the circuit utilizing the heating wire is not rigid, the accuracy of the measurement is affected by the overload or aging. Moreover, the response of the circuit is sluggish and the accuracy of the operation of the circuit is not high.

SUMMARY OF THE INVENTION It is an object of this invention to provide a novel circuit for converting the effective value of an electric quantity into a DC voltage which is simple in construction.

Another object of this invention is to provide an improved circuit for converting the effective value of an electric quantity into a DC voltage having a high response speed and a high accuracy.

According to this invention these and further objects can be accomplished by providing a circuit for converting the effective value of an input electric signal into a DC voltage comprising an integrator for producing a DC output voltage, a first means for adding the input signal to a signal fed back from the output side of the integrator, a second means for subtracting the signal fed back from the output of the integrator from the input signal, and means for multiplying the output from the first means with the output from the second means for applying the product to the input of the integrator.

The integrator has a time constant enough to sufficiently attenuate the AC component contained in the input signal. In the signal transmission circuit from the multiplier to the integrator is inserted a variable gain circuit manifesting a large gain while the input signal is smaller than a predetermined value, whereas a small gain when the input signal exceeds the predetermined value.

BRIEF DESCRIPTION OF THE DRAWINGS DESCRIPTION OF THE PREFERRED EMBODIMENTS The circuit shown in FIG. 1 comprises a multiplier M which .produces an outputcorresponding to the product of two inputs, an integrator I having a time constant CR selected to sufficiently attenuate the AC component contained in the input signals, adders A and A and a sign inversion circuit IN E, represents an input voltage and E an output voltage. The sum of the input voltage E, and output voltage with its sign inverted, E is applied to multiplier M as one of its inputs through one adder A whereas the sum of the input voltage E, and the output voltage E is applied to the other input of the multiplier through the other adder A The output from multiplier M is integrated by integrator l to produce the output voltage E The circuit shown in FIG. 1 operates as follows.

Since the output voltage (ER-E from the multiplier M is applied to integrater l, the output voltage E from the integrator l is given by an equation E =-l/CR(E,E dt Thus, the integrator I integrates the difference between the squares of input voltage E and the output voltage E As above described, as the time constant of the integrator l is sufficiently large to attenuate AC components, the output voltage E corresponds to the integrated value of the DC component of the difference (E -E Consequently, the output voltage E varies so long as the DC components of E 2 and E 2 are different, and stops to vary when the difference between DC components becomes zero.

Representing the input voltage E, by the Fourier series:

E =E+1rE sin (nwt-H9) 2 then .r... r n

2 cos 2(nwt-l-0n) +2E'En sin (nwt+0n) of the output voltage E, and the output voltage E is given by the following equation:

sin (kart-Mk) I) Since the AC components represented by the second and following lines are not included in the integrated value, the output voltage E of the integrator I reaches a definite value at a condition of Hence the output voltage E under this condition is given by The right hand term of equation 6 is expressed by the square roots of the sum of the squares of the effective values of respective components of the input voltage E which means that this term represents the effective value of the input voltage E Thus, the output voltage E of integrator I as it reaches When compared with the prior circuit wherein the input voltage is squared and then the square root of the mean value is extracted, the novel circuit is more simple in construction and when compared with the prior circuit utilizing the thermocouple the novel circuit has higher accuracies and response and is sturdy.

Considering the polarity of the feedback signal to the integrator in the basic circuit shown in FIG. 1, the positive value n .ic,

of the right hand term of equation 6 is unstable. Because, when integrator I produces a positive output voltage E and when a condition Efi-E holds true on the input side of integrator I, then if the input voltage E, varies from this condition in such direction that its absolute value decreases, a relation E, E 0 will be established on the input side of integrator I. Since, under this condition, the positive output voltage of the integrator I tends to increase the value (EB-E becomes a larger negative value on the input side of the integrator I whereby the output voltage E of the integrator I increases furthcr until a positive saturation is reached. Whereas the negative value En "v EMF 2 '2' in the right-hand term of equation 6 is a stable value not accompanying this phenomenon. Accordingly, it is suffice to obtain the stable negative value as the final output signal and the unstable positive value is not necessary.

The speed of the integrator I at which the integrator reached an equilibrium point is expressed by the 'rate of change of the output voltage E viz.,

where K represents a constant.

Assuming that the integrator I is now on the way to the equilibrium and the output voltage E is different by AE from input voltage 5,. Since the output voltage E is expressed by By substituting this relation into equation 7, we obtain the following equation representing the rate of change of the output voltageeE V QAEErjtAE?) This means that the rate of change of the output voltage E varies dependent upon the magnitude of the input voltage E,. The rate of change of the output voltage E decreases with the decrease in the input voltage E, and becomes a minimum when the input voltage becomes zero provided that the differential AE remains constant. For this reason, the speed at which the integrator I approaches the equilibrium point that is the speed of obtaining the solution becomes slower as the input voltage approaches zero so that in order to obtain sufficicntly high speed of solution it is necessary to sufficiently increase the gain of the integrator. However, when the gain of the integrator were increased to a high value, the integrator I would become saturated when the input voltage becomes high.

A modified embodiment shown in FIG. 3 includes a device for obviating this difficulty. In addition to the circuit components shown in FIG. I there are provided an operational amplifier A an input resistor R, for amplifier A serieally connected feedback resistor R and R and diodes D, and D connected in parallel position. These diodes are connected in parallel with resistor R to impart a polygonal line function characteristic to the feedback resistors. Thus, the gain of the operational amplifier circuit is high so long as the input voltage thereto is low and hence the voltage impressed across feedback resistors R and R is low so that diodes D, and D, are nonconductive, whereas the gain becomes low when the input voltage is increased to increase the voltage impressed upon feedback resistors R and R thus rendering conductive diodes D, and D,. A diode D is connected between the output terminal of integrator I and the summing junction for clamping to a small value the negative polarity output of the integrator so as to prevent integrator I from saturating in the negative direction. Furthermore, a diode D, is connected on the output side of integrator I to prevent the negative polarity output of the integrator from being fed back thus preventing the output from being unfixed. In the embodiment shown in FIG. 3, since the operational amplifier A is connected between multiplier M and integrator I, the polarity of the input voltage to integrator I becomes opposite to that of the circuit shown in FIG. I with the result that the polarity of the output that causes the undesirable alternation of the output is also opposite to that of the circuit shown in FIG. 1. Thus, in this case, the negative polarity output voltage functions to prevent the output from being unfixed.

The circuit shown in FIG. 3 operated as follows.

The output of multiplier M is amplified by the operational amplifier by a factor of its gain and is then applied to integrator I. For this reason, even the value of the input voltage E, is near zero, the speed of the operation of the integrator I is suffi ciently high. As the input voltage E, increases to increase the output voltage of multiplier M beyond a predetermined value, the gain of the operational amplifier is reduced by the polygonal line characteristic of the feedback resistors to decrease the rate of increase in the voltage applied to integrator I thereby preventing saturation thereof. Due to the function of diodes D and D,,, the output voltage E of only the positive polarity is produced from integrator I, thus removing unstability. For this reason, the circuit shown in FIG. 3 operates stably at a high speed.

When the frequency of the input voltage E, is low and the time constant alone is not enough to sufficiently attenuate the AC components, a capacitor may be added to the feedback circuit of the operational amplifier A to impart a suitable first-order-lag characteristic.

While the invention has been shown and described in terms of some preferred embodiments many changes and modifications will occur to those skilled in the art within the true spirit and scope of the invention as defined in the appended claims.

What is claimed is:

I. A circuit for converting the effective value of an input electric signal into a DC voltage, comprising an integrator for producing a DC output voltage, a first means for adding said input signal to a signal fed back from the output side of said integrator, a second means for subtracting said signal fed back from the output of said integrator from said input signal, and means for multiplying the output from said first means with the output from said second means for applying the product to the input of said integrator.

2. The circuit as defined in claim I wherein said integrator has a characteristic to sufficiently attenuate the AC component contained in the input to said integrator.

3. The circuit as defined in claim I wherein said integrator includes means for preventing the flow of an output signal of a predetermined polarity.

4. The circuit as defined in claim I wherein said integrator further comprises means for clamping the output signal of said predetermined polarity to a sufficiently small value.

5. The circuit as defined in claim 1 wherein a variable gain circuit is inserted in the signal transmission circuit from said multiplier means to said integrator, said variable gain circuit manifesting a large gain while said input signal is smaller than a predetermined value whereas a small gain when said input signal exceeds said predetermined value.

6. The circuit as defined in claim 2 wherein a variable gain circuit is inserted in the signal transmission circuit from said multiplier means to said integrator, said variable gain circuit manifesting a large gain while said input signal is smaller than a predetermined value whereas a small gain when said input signal exceeds said predetermined value.

7. The circuit as defined in claim 3 wherein a variable gain multiplier means to said integrator, said variable gain circuit manifesting a large gain while said input signal is smaller than a predetermined value whereas a small gain when said input signal exceeds predetermined value.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Da March 28, 1972 Patent No. I 3!652r945 i fl Hisao Nakane and Akihisa. Hashimoto It: is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column 2, line 13, the equation "E =E+1rE sin(nwt+e)" should read E =E+ E sin(nwt+6 Column 6, line 12, before the word "predetermined" insert the word said Signed ahd sealed this 25th day of July 1972.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. ROBERT GOTISCHALK Attesting Officer Commissioner of Patents 

1. A circuit for converting the effective value of an input electric signal into a DC voltage, comprising an integrator for producing a DC output voltage, a first means for adding said input signal to a signal fed back from the output side of said integrator, a second means for subtracting said signal fed back from the output of said integrator from said input signal, and means for multiplying the output from said first means with the output from said second means for applying the product to the input of said integrator.
 2. The circuit as defined in claim 1 wherein said integrator has a characteristic to sufficiently attenuate the AC component contained in the input to said integrator.
 3. The circuit as defined in claim 1 wherein said integrator includes means for preventing the flow of an output signal of a predetermined polarity.
 4. The circuit as defined in claim 1 wherein said integrator further comprises means for clamping the output signal of said predetermined polarity to a sufficiently small value.
 5. The circuit as defined in claim 1 wherein a variable gain circuit is inserted in the signal transmission circuit from said multiplier means to said integrator, said variable gain circuit manifesting a large gain while said input signal is smaller than a predetermined value whereas a small gain when said input signal exceeds said predetermined value.
 6. The circuit as defined in claim 2 wherein a variable gain circuit is inserted in the signal transmission circuit from said multiplier means to said integrator, said variable gain circuit manifesting a large gain while said input signal is smaller than a predetermined value whereas a small gain when said input signal exceeds said predetermined value.
 7. The circuit as defined in claim 3 wherein a variable gain circuit is inserted in the signal transmission circuit from said multiplier means to said integrator, said variable gain circuit manifesting a large gain while said input signal is smaller than a predetermined value whereas a small gain when said input signal exceeds said predetermined value.
 8. The circuit as defined in claim 4 wherein a variable gAin circuit is inserted in the signal transmission circuit from said multiplier means to said integrator, said variable gain circuit manifesting a large gain while said input signal is smaller than a predetermined value whereas a small gain when said input signal exceeds predetermined value. 